The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based memory.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. SRAMs are mainly used in applications that require a high random access speed and/or a CMOS logic compatible process. DRAMs, on the other hand, are mainly used for high-density applications where the slow random access speed of DRAM can be tolerated.
Some SRAM cell designs are based on NDR (Negative Differential Resistance) devices. They usually consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. One advantage of the NDR-based cell is the potential of having a cell area smaller than conventional SRAM cells (e.g., either 4T or 6T cells) because of the smaller number of active devices and interconnections. Many of the NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. Some of these problems include: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A novel type of NDR-based SRAM (xe2x80x9cthin capacitively-coupled thyristor RAMxe2x80x9d) has been recently introduced that can potentially provide the speed of conventional SRAM at the density of DRAM in a CMOS compatible process. This new SRAM cell uses a thin capacitively-coupled NDR device and more specifically a thin capacitively-coupled thyristor to form a bistable element for the SRAM cell. For more details of specific examples of this new device, reference may be made to: xe2x80x9cA Novel High Density, Low Voltage SRAM Cell With A Vertical NDR Device,xe2x80x9d VLSI Technology Technical Digest, June, 1998; xe2x80x9cA Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,xe2x80x9d International Electron Device Meeting Technical Digest 1999, and xe2x80x9cA Semiconductor Capacitively-Coupled NDR Device And Its Applications For High-Speed High-Density Memories And Power Switches,xe2x80x9d PCT Int""l Publication No. WO 99/63598, corresponding to U.S. patent application Ser. No. 09/092449, now U.S. Pat. No. 6,229,161 (Nemati, et al.). Each of these documents is incorporated by reference in its entirety.
An important design consideration in any type of thyristor-based memory cell, including a thin capacitively-coupled thyristor RAM cell, is the holding current of the thyristor. The holding current of the thyristor is the minimum current that keeps the thyristor in the forward conducting state. This holding current has to be sufficiently low so that the memory cell has an acceptable standby current. For example, a holding current larger than a few nano-Amperes per cell could significantly limit the maximum capacity of a thyristor-based memory.
Another important consideration when using a thyristor-based memory cell is the sensitivity of the blocking state of the thyristor to various adverse conditions such as noise, light, anode-to-cathode voltage changes and high temperatures. These sensitivities can affect the operation of the thyristor, resulting in undesirable turn-on, which disrupts the contents of the memory cell.
The present invention is directed to a thyristor-based memory device and approach, including those specific examples discussed and incorporated above, that address the above-mentioned challenges. A particular aspect of the present invention is directed to a thyristor-based memory approach that overcomes one or more of the above-mentioned adverse conditions without significantly increasing the holding current of the thyristor and thereby preventing an unacceptable increase in standby current of the memory cell. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to one example embodiment, the present invention is directed to using a thyristor device having a capacitively-coupled control port to control data access (read and/or write) to a data-storage memory circuit in a semiconductor device, so that the thyristor device does not switch on inadvertently. The thyristor device""s capacitively-coupled control port is used to switch the thyristor device between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states and thereby provide write access to the data-storage memory circuit. So that the thyristor device does not switch on inadvertently due to an adverse condition such as high temperature, noise, a very rapid anode-cathode voltage change, or light, the method includes shunting low-level current at the base region in at least one of the thyristor device""s anode or cathode end portions.
According to another example embodiment, the present invention is directed to a semiconductor device that includes a thyristor-based memory. The device includes a control port capacitively coupled to a first one of either an anode or cathode end portion of the thyristor. Each of the end portions includes an emitter region and an adjacent base region, and a current shunt region is located between the emitter and base region of a second one of the end portions. A current shunt region is configured and arranged to shunt low-level current between the emitter region and the adjacent base region in a manner that improves the stability of the semiconductor device under operating conditions including high temperature, voltage, light, noise and other disturbances.
According to another example embodiment of the present invention, a current shunt that includes a tunneling current component is located near the base junction of a thyristor and is used to shunt current to the base region. The tunneling current is implemented in various forms, depending upon the particular application. In one instance, the diode includes a heavily doped region between the base and emitter regions, and in another instance includes a tunneling dielectric adjacent and between the base region and a tunnel node. In either instance, the tunneling current shunts excess current that can result from adverse operating conditions, such as those described hereinabove.
The present invention provides other advantageous implementations including, for example, specific placement of the means for shunting low-level current and various types of effective shunting devices.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.